The present disclosure relates to semiconductor devices having multilayer interconnect structures.
As an example of multilayer interconnect structures of semiconductor devices, Japanese Patent Publication No. 2001-160591 discloses a configuration in which via contacts are provided on a pair of adjacent lower-layer interconnects such that the via contacts are offset relative to each other in the interconnect direction. In semiconductor processes of recent years, in order to reduce interconnect delay, the technique of purposely forming a pore in an insulating material provided between interconnects is used to reduce the relative dielectric constant between the interconnects. The technique of Japanese Patent Publication No. 2001-160591 prevents defects due to short-circuiting in multilayer interconnect structures having a pore purposely formed in an insulating layer between interconnects.